1. Field of the Invention
The present invention relates generally to a semiconductor device. More particularly, the invention relates to a semiconductor device having a plurality of input/output cell areas.
2. Description of the Related Art
One demand for highly integrated semiconductor devices is to increase external connection pins which are associated with a plurality of circuits in a semiconductor chip. The external connection pins are connected to input/output (I/O) external pads located on the peripheral area of a semiconductor chip along the edges of the semiconductor chip. It is therefore necessary to shorten the pitch between the adjacent I/O external pads. The individual I/O external pads are also connected to associated input/output circuits. Each input/output circuit is located in an associated one of a plurality of I/O cell areas defined on the peripheral area of the semiconductor chip inward of the associated I/O external pad. It is thus necessary to reduce the widths of the I/O cell areas or the lengths of the I/O cell areas extending along the edges of the semiconductor chip.
FIG. 1 shows a conventional output circuit 101 provided in one I/O cell area 100 on a CMOS gate array. The output circuit 101 includes four nMOS transistors 102 and four pMOS transistors 103. The portions of the nMOS transistors 102 and the pMOS transistors 103 illustrated in FIG. 1 are the gates of the individual MOS transistors.
Each pair of the nMOS transistor 102 and the pMOS transistor 103 are arranged in a row along (or in the lengthwise direction of) the I/O cell area 100. Specifically, the gate, source and drain (the source and drain not shown) of each nMOS transistor 102 are formed to extend along (or in the lengthwise direction of) the I/O cell area 100. The gate, source and drain (the source and drain not shown) of each pMOS transistor 103 are also formed to extend along the I/O cell area 100.
First aluminum lines 104 are located over the sources of the respective nMOS transistors 102. Each first aluminum line 104 is formed in a first metal interconnection layer so as to extend along the associated I/O cell area 100. Located over the first aluminum lines 104 is a first aluminum power line 106 to which a low-potential supply voltage (V.sub.SS) is supplied. The first aluminum power line 106 is formed in a second metal interconnection layer so as to extend across (or in the width direction of) the associated I/O cell area 100. The sources of the individual nMOS transistors 102 are electrically connected to the first aluminum power line 106 via the associated first aluminum lines 104.
Second aluminum lines 105 are located over the sources of the respective pMOS transistors 103. Each second aluminum line 105 is formed in the first metal interconnection layer so as to extend along the associated I/O cell area 100. Located over the second aluminum lines 105 is a second aluminum power line 107 to which a high-potential supply voltage (V.sub.DD) is supplied. The second aluminum power line 107 is formed in the second metal interconnection layer so as to extend across the associated I/O cell area 100. The sources of the individual pMOS transistors 103 are electrically connected to the second aluminum power line 107 via the associated second aluminum lines 105.
Third aluminum lines 108 are located over the drains of the nMOS transistors 102 and the pMOS transistors 103. Each third aluminum line 108 is formed in a first metal interconnection layer so as to extend along the associated I/O cell area 100. The drains of the nMOS transistors 102 and the pMOS transistors 103 are electrically connected to the respective external pad (not shown) via the associated third aluminum lines 108.
As mentioned above, multiple first to third aluminum lines 104, 105 and 108 and also gate contact lines (not shown) are formed in the first metal interconnection layer so as to extend along the I/O cell areas 100. This makes it difficult to reduce the widths CW0 of the I/O cell areas 100.
It is also necessary to provide sufficient intervals between the third aluminum line 103 and the first and second aluminum lines 104 and 105 to avoid the mutual contact. The third aluminum lines 108 have relatively wide widths W0 to improve the electromigration resistance. The restrictions on the first to third aluminum lines 104, 105 and 108 lead to an increase in the widths CW0 of the I/O cell areas 100. As a result, it is difficult to shorten the pitch between the adjoining I/O cell areas 100. In other words, the pitch between the adjoining I/O cell areas 100 becomes greater than the pitch between the adjoining pads.
Thus, there is a need for a semiconductor device having reduced pitch between I/O cell areas.